JTAG/Boundary Scan tests

                                                                             JTAG/Boundary Scan
JTAG(Joint Test Action Group)is an international standard Test protocol (IEEE 1149.1 compatible), mainly used for chip internal testing. Now the most advanced devices support JTAG protocol, such as DSP, FPGA devices, etc.

1,Boundary Scan
   a) BSDL validation
   b) Test program debugging
   c) Hardware debugging
   d) Testability optimization
   e) Fault coverage improvement

2,Structural test
   a) infrastructure test  b) connection test
  c) i/o connection test
  d) boundary scan/flying probe test
  e) RAM access
  f) logic cluster test
  g) components i/o test
  h) Analog I/o test
  i) currentless open/short test
  k) built-in self-test
  l) FPGA-assisted RAM access test
  m) FPGA-assisted bit error rate test(BERT)
  n) Universal frequency measurement

3,functional/emulation tests

    a) internal chip test
    b) cluster test
    c) board-i/o-test
    d) Core-assisted RAM access test
    e) Core-assisted system bus test
    f)  Core-assisted i/o test

4,programming of components
  a) PLD/FPGA programming
  b) Boundary Scan flash programming
  c) Micro contraller programming
  d) C0re-assisted flash programming
  e) FPGA-assisted flash programming